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tiny i 2 c programmable linear battery charger with power path and usb mode c ompatibility data sheet adp5061 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.31 13 ? 2012 analog devices, inc. all rights reserved. features 2.6 mm 2 mm wlcsp p ackage fully programmable via i 2 c flexible digital control inputs up to 2.1 a current from an ac charger in ldo mode operating input voltage from 4.0 v to 6.7 v tolerant input voltage from ? 0.5 v to + 20 v (usb vbus) fully compatible with usb 3.0 and usb battery charging s pecification 1.2 built - in current sensing and limiting as low as 30 m battery isolation fet between battery and charger output thermal regulation prevents over heating compliant with jeita 1 and jeita 2 li - ion battery charging temperature specifications sys_en flag permits the system to be disabled until battery is at minimum required level for guaranteed system start - up applications digita l still cameras digital video cameras single c ell li - ion portable equipment pdas, a udio, and gps d evices portable medical devices mobile p hones t ypical a pplication c ircuit figure 1. general description the adp5061 charger is fully compliant with usb 3.0 and the usb battery charging specification 1.2 and enables charging via the mini usb vbus pin from a wall charger, car charger, or usb h ost port. the adp5061 operates from a 4 v to 6.7 v input voltage range but is tolerant of voltages up to 20 v. th e 20 v voltage tolerance alleviates the concerns about the usb bus spiking during dis - connect or connect scenarios. the adp5061 features an inte rnal fet between the linear charger output and the battery. this permits battery isolation and , hence , system powering under a dead battery or no battery scenario, which allows for immediate system func tion on connec - tion to a usb power supply. based on the type of usb source, which is detected by an external usb det ection chip, the adp5061 can be set to apply the correct current limit for optimal charging and usb compliance. the adp5061 has three factory programmable digital input/output pins that provide maximum flexibility for different systems. th ese digital input/out put pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits , and a dedicated interrupt output pin. vin vbus ac or usb scl sda dig_io1 dig_io2 dig_io3 agnd + li-ion thr c3 47 f c2 10nf c1 10 f c4 22 f iso_s iso_b bat_sns adp5061 sys_en system programmable iled vled cbp charger control block 10544-001
adp5061 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 recommended input and output capacitances ...................... 6 i 2 c- compatible interface timing specifications ..................... 6 absolute maximum ratings ....................................................... 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 temperature characteristics ..................................................... 11 typical waveforms ..................................................................... 13 theory of operation ...................................................................... 14 summary of operation modes ................................................. 14 introduction ................................................................................ 15 charger modes ............................................................................ 17 thermal management ............................................................... 20 battery isolation fet ................................................................. 20 battery detection ....................................................................... 20 batt ery pack temperature sensing .......................................... 21 i 2 c interface ................................................................................ 25 i 2 c register map ......................................................................... 26 register bit descriptions ........................................................... 27 ap plications information .............................................................. 35 external components ................................................................ 35 pcb layout guidelines .............................................................. 37 power dissipation and thermal considerations ....................... 38 charger power dissipation ....................................................... 38 ju nction temperature ................................................................ 38 factory programmable options ................................................... 39 charger options ......................................................................... 39 i 2 c register defaults .................................................................. 40 digital input and output options ........................................... 40 packaging and ordering information ......................................... 42 outline dimensions ................................................................... 42 ordering guide .......................................................................... 42 re vision history 6/ 12 rev ision 0: initial version
data sheet adp5061 rev. 0 | page 3 of 44 specifications ? 40 c < t j < + 125c, v vin = 5.0 v, v hot < v thr < v cold , v bat_sns = 3.6 v, v iso_b = v bat_sns , c vin = 10 f, c iso_s = 22 f, c iso_b = 22 f, c c bp = 10 nf , all registers at default values, unless otherwise noted . table 1 . parameter symbol min typ max unit test conditions/comments general parameters undervoltage locko ut v uvlo 2.25 2.35 2.5 v falling threshold, higher of v vin and v bat_sns 1 hysteresis 50 100 150 mv hysteresis, higher of v vin and v bat_sns rising 1 total input current i lim 74 92 100 ma nominal usb initialized current level 2 114 150 ma usb super speed 300 ma usb enumerated current level ( s pecification for china) 425 47 0 500 ma usb enumerated current level 900 ma dedicated charger input 1500 ma dedicated wall charger vinx current consumption i qvin 2 ma charging or ldo mode i qvin_dis 280 450 a dis_ic1 = high, v iso_b < vinx < 5.5 v battery current consumption i qbatt 20 a ldo mode, v iso_s > v bat_sns 5 a standby, includes iso_sx pin leakage, v vin = 0 v, t j = ?40c to +85c 0.5 0.9 ma standby, b attery monitor active charger fast charge current cc mode i chg 715 750 775 ma v iso_b = 3.9 v ; f ast charge current accuracy is guaranteed at temperatures from t j = ? 40c to i sothermal regulation limit (typically t j = + 115c) 2 , 3 fast charge current accuracy ? 40 +30 ma i chg = 50 ma to 550 ma ? 50 +30 ma i chg = 600 ma to 950 ma ?65 +35 ma i chg = 1000 ma to 1300 ma trickle charge current 2 i trk_dead 16 20 25 ma weak charge current 2 , 3 i chg_weak i trk_dead + i chg ma trickle to weak charge threshold dead battery v trk_dead 2.4 2.5 2.6 v v trk_dead < v bat_sns < v weak 2 , 4 hysteresis v trk_dead 100 mv on bat_sns 2 weak battery threshold weak to fast charge threshold v weak 2.89 3.0 3.11 v on bat_sns 2 , 4 v weak 100 mv battery termination voltage v trm 4.200 v termination voltage accuracy ?0.25 +0.25 % on bat_sns, t j = 25c, i end = 52.5 ma 2 ?0.96 +0.89 % t j = 0c to 115c 2 ?1.15 +1.20 % t j = ? 40c to + 125c battery overvoltage threshold v batov v in ? 0.075 v relative to vinx voltage, bat_sns rising charge complete current i end 15 52.5 98 ma v bat_sns = v trm charging complete current threshold accuracy 17 83 ma i end = 52.5 ma , t j = 0c to 115c 2 59 123 i end = 92.5 ma , t j = 0 c to 115c recharge voltage differential v rch 160 260 390 mv relative to v trm , bat_sns falling 2 battery node short threshold voltage 2 v bat_shr 2.2 2.4 2.5 v battery short detection current i trk_short 20 ma i trk_short = i trk_dead 2 charging start voltage limit v chg_vlim 3.6 3.7 3.8 v voltage limit is not active by default charging soft start current i chg_start 185 260 365 ma v bat_sns > v trk_dead charging soft start timer t chg_start 3 ms battery isolation fe t bump to bump resistance between iso_sx and iso_bx r dsoniso 30 49 m o n battery supplement mode, vinx = 0 v, v iso_b = 4.2 v , i iso_b = 500 ma regulated system voltage: v bat low v iso_sfc 3.6 3.8 4.0 v vtrm [5:0] programming 4.00 v 3.3 3.5 3.7 vtrm [5:0] programming < 4.00 v battery supplementary threshold v thiso 0 5 12 mv v iso_s < v iso_b , v sys rising
adp5061 data sheet rev. 0 | page 4 of 44 parameter symbol min typ max unit test conditions/comments ldo and high voltage blocking regulated system voltage v iso_strk 4.214 4.3 4.386 v vsystem [2:0] = 000 (binary) = 4.3 v, i iso_s = 100 ma, ldo mode 2 load regulation ? 0.28 %/a i iso_s = 0 m a to 1 5 00 ma high voltage blocking fet (ldo fet) on resistance r ds(on)hv 3 30 485 m i v in = 500 ma maximum output current 2.1 a v iso_s = 4.3 v, ldo mode vinx input voltage, good threshold rising v vin_ok_rise 3.75 3.9 4.0 v vinx falling v vin_ok_fall 3.6 3.7 v vinx input overvoltage threshold v vin_ov 6.7 6.9 7.2 v hysteresis v vin_ov 0.1 v vinx transition timing t vin_rise 10 s minimum rise time for vinx from 5 v to 20 v t vin_fall 10 s minimum fall time for vinx from 4 v to 0 v thermal control isothermal charging temperature t lim 115 c thermal early warning temperature t sdl 130 c thermal shutdown temperature t sd 140 c t j rising 110 c t j falling thermistor control thermistor current 10,000 ntc i ntc_10k 400 a 100,000 ntc i ntc_100k 40 a thermistor capacitance c ntc 100 pf cold temperature threshold t ntc_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 hot temperature threshold t ntc_hot 60 c no battery charging occurs resistance thresholds hot to typical resistance r hot_fall 3700 typical to hot resistance r hot_rise 2750 3350 3950 jeita1 l i- ion battery charging specification defaul ts 5 jeita cold temperature t jeita_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 jeita cool temperature t jeita_cool 10 c battery charging occurs at 50% of programmed level resistance thresholds typical to cool resistance r typ_fall 13,200 16,500 19,800 cool to typical resistance r typ_rise 15,900 jeita typical temperature t jeita_typ c normal battery charging occurs at default/programmed levels resistance thresholds warm to typical resistance r warm_fall 5800 typical to warm resistance r warm_rise 4260 5200 6140 jeita warm temperature t jeita_warm 45 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds hot to warm resistance r hot_fall 3700 warm to hot resistance r hot_rise 2750 3350 3950 jeita hot temperature t jeita_hot 60 c no battery charging occurs
data sheet adp5061 rev. 0 | page 5 of 44 parameter symbol min typ max unit test conditions/comments jeita2 l i- ion battery charging specification defaul ts 5 jeita cold temperature t jeita_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 jeita cool temperature t jeita_cool 10 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds typical to cool resistance r typ_fall 13,200 16,500 19,800 cool to typical resistance r typ_rise 15,900 jeita typical temperature t jeita_typ c normal battery charging occurs at default/programmed levels resistance thresholds warm to typical resistance r warm_fall 5800 typical to warm resistance r warm_rise 4260 5200 6140 jeita warm temperature t jeita_warm 45 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds hot to warm resistance r hot_fall 3700 warm to hot resistance r hot_rise 2750 3350 3950 jeita hot temperature t jeita_hot 60 c no battery charging occurs battery detection battery detection sink current i sink 13 20 34 ma source current i source 7 10 13 ma battery threshold low v batl 1.8 1.9 2.0 v high v bath 3.4 v battery detection timer t batok 333 ms timers clock oscillator frequency f clk 2.7 3 3.3 mhz start charging delay t start 1 s ec trickle charge t trk 60 min fast charge t chg 600 min charge complete t end 7.5 min v bat_sns = v trm , i chg < i end deglitch t dg 31 ms applies to v trk , v rch , i end , v dead , v vin_ok watchdog 2 t wd 32 sec safety t safe 36 40 44 min battery short 2 t bat_shr 30 sec iled output pin s voltage drop o ver iled v iled 200 mv i iled = 20 ma maximum operating voltage over iled v maxiled 5.5 v sys_en output pin sys_en fet on resistance r on_sys_en 10 i sys_en = 20 ma logic input pin maximum voltage on digital inputs v din_max 5.5 v applies to scl, sda, dig_io1, dig_io2, dig_io3 maximum logic low input voltage v il 0.5 v applies to scl, sda, dig_io1, dig_io2, dig_io3 minimum logic high input voltage v ih 1.2 v applies to scl, sda, dig_io1, dig_io2, dig_io3 pull - down resistance 215 350 610 k applies to dig_io1, dig_io2, dig_io3 1 undervoltage lockout generated normally from iso_sx or iso_bx ; in certain transition cases , it can be generated from vinx . 2 these values are programmable via i 2 c. values are given with default register values. 3 the output current during charging may be limited by the input current limit or by the isothermal charging mode. 4 during weak charging mode, the charger provides at least 20 ma of charging current via the trickle charge bra nch to the battery unless trickle charging is disabled. any residual current, which is not required by the system , is also used to charge the battery. 5 either jeita1 (default) or jeita2 can be selected in i 2 c, or both jeita functions can enabled or disabl ed in i 2 c.
adp5061 data sheet rev. 0 | page 6 of 44 recommended input an d output capacitance s table 2 . parameter symbol min typ max unit test conditions/comments capacitances vinx c vin 4 10 f effective capacitance cbp c bp 6 10 14 nf effective capacitance iso_sx c iso_s 20 47 100 f effective capacitance iso_bx c iso_b 10 22 f effective capacitance i 2 c- compatible interface timing specification s table 3 . parameter 1 symbol min typ max unit test conditions/comments i 2 c- compatible interface 2 capacitive l oad for each bus line c s 400 pf scl clock frequency f scl 400 khz scl high time t high 0.6 s scl low time t low 1.3 s data setup time t su , dat 100 ns data hold time t hd , dat 0 0.9 s setup t ime for repeated start t su , sta 0.6 s hold t ime for start/repeated start t hd , sta 0.6 s bus free time between a s top and a s tart c ondition t buf 1.3 s setup t ime for stop condition t su , sto 0.6 s rise t ime of scl/sda t r 20 300 ns fall t ime of scl/sda t f 20 300 ns pulse w idth of suppressed spike t sp 0 50 ns 1 guaranteed by design. 2 a master device must provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the falling edge of scl (see figure 2 ). timing diagram figure 2 i 2 c timing diagram sd a s = s t art condition sr = repe a ted s t art condition p = s top condition scl s sr p s t low t su, dat t hd, sta t bu, sto t hd, dat t bu, sta t high t r t f t r t f t sp t buf 10544-002
data sheet adp5061 rev. 0 | page 7 of 44 absolute maximum rat ings table 4 . absolute maximum ratings parameter rating vin1, vin2, vin3 to agnd C 0.5 v to +20 v all other pins to agnd C 0.3 v to +6 v continuous drain current, battery supple - mentary mode, from iso_bx to iso_sx 2.1 a storage temperature range C 65c to +150c operating junction temperature range C 40c to +125c soldering conditions jedec j - std -020 thermal resistance ja is specified for the worst - case conditions, that is, ja is specified for a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc jb unit 20 - lead wlcsp 1 46.8 0.7 9.2 c/w 1 5 4 array, 0.5 mm pitch (2.6 mm 2.0 mm); based on a jedec 2s2p, 4 - layer board with 0 m/sec airflow. maximum power dissipation the maximum safe power dissipation in the adp5061 package is limited by the associated rise in junction temperature (t j ) on the die. at a die temperature of approximately 150 c ( the glass transition temperature ), the properties of the plastic change . even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby perma - nently shifting the parametric performance of the adp5061 . exceeding a junction temper ature of 175 c for an extended period can result in changes in the silicon devices , potentially causing failure. esd caution stress es a bo ve thos e l isted under absolute maxim um ratin gs ma y c ause permanent damage to the device. this is a stress rating only; fu nctional operation of the d ev ice at these or any other co nditio ns abo ve those indicated in the operatio na l section of th is speci fi cat ion is not implied. expo su re to absolu te ma ximum rat in g conditions fo r e xtended periods may a ff ect de vi ce reliability.
adp5061 data sheet rev. 0 | page 8 of 44 pin configuration and function descripti ons figure 3. pin configuration table 6 . pin function descriptions pin no. name type 1 description e2, d2, c2 iso_s1, iso_s2, iso_s3 i/o linear charger supply side input to t he internal isolation fet/ battery current regulation fet. h igh current input/output. e3, d3, c3 vin1, vin2, vin3 i/o power c onnections to usb vbus. these pins are high current inputs when in charging mode. b1 agnd g analog g round. e1, d1, c1 iso_b1, iso_b2, iso_b3 i/o battery supply side input to internal isolation fet/ battery current regulation fet. a4 scl i i 2 c- compatible interface serial clock . a3 sda i/o i 2 c- compatible interface serial data . e4 dig_io1 gp io set input current limit. this pin sets the input current limit directly. when dig_io1 = low or high - z, the input limit is 100 ma. when dig_io1 = high, the input limit is 500 ma. 2 , 3 c4 dig_io2 gp io disable ic1. this pin sets the charger to the low current mode. when dig_io2 = low or high - z, the charger operates in normal mode. when dig_io 2 = high, the ld o and the charger are disabled and vinx current consumption is 280 a (typical) . 20 v vinx input protection is disabled and vinx voltage level must be equal to or lower than 5.5 v. 2 , 3 b4 dig_io3 gp io enable charging. when dig_io3 = low or high - z, charging is disabled. when dig_io3 = high, charging is enabled . 2 , 3 b2 thr i batte ry pack thermistor connection . if this pin is not used, connect a dummy 10 k resistor from thr to gnd. d4 bat_sns i battery voltage sense pin. a1 iled o open -d rain o utput to i ndicator led. a2 sys_en o system enable. this is the b attery ok flag /open - drain pull - down fet pin to enable the system when the battery level reache s the v weak level. b3 cbp i/o bypass capacitor input. 1 i is input, o is output, i/o is input/output, g is ground, and gpio is factory programmable general - purpose input/output. 2 see the digital input and output options section for details. 3 dig_iox setting defines the initial state of th e adp5061 . when the parameter or the mode that is related to each dig_iox pin setting is changed (by programming the equivalent i 2 c register bit or bits ), the i 2 c register setting dominate s over the dig_iox pin setting . vinx connection or disconn ection resets control to the dig_iox pin . top view (ball side down) not to scale 1 a b c d e 2 3 4 ball a1 corner iled agnd iso_b3 iso_b2 sda cbp vin3 vin2 scl dig_io3 dig_io2 bat_sns sys_en thr iso_s3 iso_s2 iso_b1 vin1 dig_io1 iso_s1 10544-003
data sheet adp5061 rev. 0 | page 9 of 44 typical performance characteristics v vin = 5.0 v, c vin = 10 f, c iso_s = 44 f, c iso_b = 22 f, c bp = 10 nf , all registers at default values, unless otherwise noted. figure 4 . system voltage vs. system output current, ldo mode, vsystem [2:0] = 000 (b inary) = 4.3 v figure 5 . output voltage vs. input voltage (in dropout), ldo mode, vsystem [2:0] = 000 ( b inary) = 4.3 v figure 6 . input current - limited charge current vs. battery voltage figure 7 . system voltage vs. system output current, ldo mode, v vin = 6.0 v, vsystem [2:0] = 111 (binary) = 5.0 v figure 8 . output voltage vs. input voltage (in dropout), ldo mode, vsystem [2:0] = 111 (b in ary) = 5.0 v figure 9 . battery charge current vs. battery voltage, ichg [4:0] = 01001 (binary) = 500 ma, ilim [3:0] = 1111 (binary) = 2100 ma 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 0.01 0.1 1 system vo lt age (v) system output current (a) 10544-004 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 system voltage (v) input vo lt age (v) load = 100ma load = 500ma load = 1000ma 10544-005 0 100 200 300 400 500 600 700 800 900 1000 2.7 3.2 3.7 4.2 charge current (ma) ba tte ry vo lt age (v) limit = 900ma limit = 500ma limit = 100ma 10544-006 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0.01 0.1 1 system vo lt age (v) system output current (a) 10544-007 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 system vo lt age (v) input vo lt age (v) load = 100ma load = 500ma load = 1000ma 10544-008 0 100 200 300 400 500 600 700 2.3 2.8 3.3 3.8 4.3 charge current (ma) ba tte ry vo lt age (v) weak charge fast charge trickle charge 10544-009
adp5061 data sheet rev. 0 | page 10 of 44 figure 10 . ideal diode r on vs. battery voltage, i iso_s = 500 ma, vin x o pen figure 11 . vinx current vs. vinx voltage figure 12 . i deal diode r on vs. load current, v iso_b = 3.6 v figure 13 . charge profile, ilim [3:0] = 0110 (binary) = 500 ma, battery capacity = 925 mah 20 22 24 26 28 30 32 34 36 38 40 2.7 3.2 3.7 4.2 isolation fet resistance (m?) battery voltage (v) 10544-010 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2 4 6 8 vinx current (ma) input voltage (v) default startup dis_ldo = high dis_ic1 = high 10544-0 11 20 22 24 26 28 30 32 34 36 38 40 0 0.5 1.0 1.5 2.0 isolation fet resistance (m?) load current (a) 10544-012 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 0 50 100 150 charge current (a) battery voltage (a) charge time (min) v bat_sns i iso_b 10544-013
data sheet adp5061 rev. 0 | page 11 of 44 temperature characte ristics figure 14 . battery leakage current vs . amb ient temperature figure 15 . vinx q uiescent current vs. ambient temperature , dis_ic1 = h igh figure 16 . ldo mode voltage vs. ambient temperature, load = 100 ma, v vi n = 5.5 v figure 17 . system voltage vs. t emperature, trickle charge mode, v iso_s = 4.3 v and vinx = 5.0 v, or v iso_s = 5.0 v and vinx = 6.0 v figure 18 . vinx q uiescent current vs. ambient temperature , ldo mode figure 19 . termination voltage vs . ambient temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 ?40 ?15 10 35 60 85 st andb y current (a) ambient temper a ture (c) v iso_b = 3.6v v iso_b = 4.2v v iso_b = 5.5v 10544-014 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vinx quiescent current (ma) ambient temper a ture ( c) v in = 4.0v v in = 5.0v v in = 5.5v 10544-015 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 system vo lt age accurac y (%) ambient temper a ture ( c) v iso_s = 4.3v v iso_s = 5.0v 10544-016 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 system vo lt age accurac y (%) ambient temper a ture ( c) v iso_s = 4.3v v iso_s = 5.0v 10544-017 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vinx quiescent current (ma) ambient temper a ture (c) v in = 4.0v v in = 5.0v v in = 6.7v 10544-018 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vtrm vo lt age accurac y (%) ambient temper a ture (c) v trm = 3.8v v trm = 4.2v v trm = 4.5v 10544-019
adp5061 data sheet rev. 0 | page 12 of 44 figure 20 . fast charge cc mode c urrent vs. ambient temperature figure 21 . vinx overvoltage threshold vs. ambient temperature figure 22 . input current limit vs . ambient temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ?40 ?15 10 35 60 85 110 charge current (a) ambient temper a ture ( c) i chg = 750ma i chg = 500ma i chg = 1300ma 10544-020 ambient temper a ture (c) 6.80 6.85 6.90 6.95 7.00 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vin ove rvo lt age threshold (v) 10544-021 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 input current limit (a) ambient temper a ture (c) i lim = 1500ma i lim = 900ma i lim = 500ma i lim = 100ma 10544-022
data sheet adp5061 rev. 0 | page 13 of 44 typical waveforms figure 23 . charging startup, v vin = 5.0 v, ilim [3:0] = 0110 (binary) = 500 ma, ichg [4:0] = 01110 (binary) = 750 ma figure 24 . load transient , i i so_sx l oad = 300 ma to 1500 ma to 300 ma figure 25 . i nput current - limit transition from 100 ma to 900 ma, iso_sx load = 66 ?, charging = 750 ma figure 26 . vbus disconnect figure 27 . load transient. i iso_sx l oad = 300 ma to 1500 ma to 300 ma, en_chg = h igh, ilim [3:0] = 0110 (binary) = 500 ma figure 28 . battery detection waveform , vsystem[2:0] = 000 (binary) = 4.3 v, no battery i vin i iso_b v vin v iso_s 10544-023 i iso_s v iso_s 10544-024 i iso_b v iso_s v vin i vin 10544-025 i vin i iso_b v vin v iso_s 10544-026 i iso_s i iso_b v iso_s 10544-027 i iso_b v iso_b 10544-028
adp5061 data sheet rev. 0 | page 14 of 44 theory of operation summary of operation modes table 7 . summary of the adp5061 operation modes mode name vinx c ondition battery c ondition trickle c harge ldo fet s tate battery i solation fet system v oltage iso_sx additional conditions 1 ic off, standby 0 v any battery condition off off on/off battery voltage or 0 v disable ic1 ic off, suspend 5 v any battery condition off off on b attery voltage disable ic1 ldo mode off, isolation fet on 5 v any battery condition off off on battery voltage disable ldo and enable isolation fet ldo mode off, isolation fet off (system off) 5 v any battery condition off off off 0 v enable battery charging ldo mode, charger off 5 v any battery condition o ff ldo o ff 5.0 v enable battery charging trickle charge mode 5 v battery < v trk_dead on ldo off 5.0 v enable battery charging weak charge mode 5 v v trk_dead b attery < v weak on chg chg 3.8 v enable battery charging fast charge mode 5 v battery v weak o ff chg chg 3.8 v (min) enable battery charging charge mode, no battery 5 v open off ldo off 5.0 v enable battery charging charge mode, battery (iso_bx) short 5 v short on ldo off 5.0 v enable battery charging 1 see table 8 for details. table 8 . operation mode controls pin c onfiguration dig_iox equivalent i 2 c a ddress, d ata description enable battery charging dig_io3 0x07, d0 low = all charging modes disabled (fast, weak, trickle) . high = all charging modes enabled (fast, weak, trickle) . disable ic1 dig_io2 0x07, d6 disable ic1 vinx 1 supply connected ldo_fet iso_fet low no o ff on y es chg chg high no off on yes off on disable ldo and enable isolation fet 0x07, d3, d0 low = ldo enabled . high = ldo disabled . in addition, when en_chg = low, the battery isolation fet is on ; when en_chg = high , the battery isolation fet is off. 1 when disable ic1 mode is active and the vin x supply is connected, the supply voltage level must fulfill the following condition: v iso_b < vin < 5.5 v.
data sheet adp5061 rev. 0 | page 15 of 44 introduction the adp5061 is a fully programmable i 2 c charger for single cell lithium - ion or lithium - polymer batteries suitable for a wide range of portable applications. the linear charger architecture enables up to 2.1 a output current at 4.3 v to 5.0 v (i 2 c programmable) on the system power supply , and up to 1.3 a charge current into the battery from a dedicated charger. the adp5061 operates from an input voltage of 4 v up to 6.7 v but is tolerant of voltages of up to 20 v. the 20 v voltage tolerance alleviates the concerns of the usb bus spiking during discon - nection or connection scenarios. the adp5061 features an int ernal fet between the linear charger output and the battery. this feature permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function up on connection to a usb power supply. the adp5061 is fully compliant with usb 3.0 and the usb battery charging specification 1.2 . the adp5061 is chargeable via the mini usb vbus pin from a wall charger, car charger, or usb hos t port. based on the type of usb source, which is detected by an external usb detection device, the adp5061 can be set to apply the correct current limit for optimal charging and usb com pliance. the usb charger permits correct operation under all usb - compliant sources such as wall chargers, host chargers, hub chargers, and standard host and hubs. a processor can control the usb charger using the i 2 c to program the charging current and num erous other parameters , including ? trickle charge current level ? t rickle charge voltage threshold ? weak charge (constan t current) current level ? fast charge (constant current) current level ? fast charge (constant voltage) voltage level at 1% accuracy ? fast charge safety timer period ? w atchdog safety timer parameters ? weak battery thr eshold detection ? charge complete threshold ? recharge threshold ? charge enable/disable ? battery pack temperature detection and automatic charger shutdown
adp5061 data sheet rev. 0 | page 16 of 44 figure 29 . block diagra m e3 d3 d3 e3 iso_s1 iso_s2 iso_s3 vin1 vin2 c3 c1 iso_b2 b2 thr + ? 0.5v ntc current control cold cool warm hot ntc trickle current source b3 battery detection sink d4 bat_sns battery detection battery: open short trickle weak cv-mode recharge charge control eoc to system load + ? 6.85v 3.9v + ? + ? + ? + ? + ? + ? + ? + ? vin overvoltage vin limit battery isolation fet vin good battery overvoltage a4 a3 scl sda to usb vbus or wall adapter b1 agnd e4 c4 b4 dig_io1 dig_io2 dig_io3 a2 sys_en 3mhz osc single cell li-ion tsd 140c sys_en output logic thermal control c3 vin3 cbp iso_b3 d1 e1 a1 iled iled output logic high voltage blocking ldo-fet + ? ldo-fet control 3.4v i 2 c interface and control logic vin ? 150mv iso_b1 1.9v warning 130c isothermal 115c tsd down 110c 10544-029
data sheet adp5061 rev. 0 | page 17 of 44 the adp5061 includes a number of significant features to optimize charging and functionality including ? thermal regulation for maximum performance ? usb host current-limit accuracy: 5%. ? termination voltage accuracy: 1%. ? battery thermistor input with automatic charger shutdown in the event that the battery temperature exceeds limits (compliant with the jeita li-ion battery charging temperature specification). ? three external pins (dig_io1, dig_io2, and dig_io3) that directly control a number of parameters. these pins are factory programmable for maximum flexibility. they can be factory programmed for functions such as ? enable/disable charging. ? control of 100 ma or 500 ma input current limit. ? control of 1500 ma input current limit. ? control of the battery charge current. ? interrupt output pin. see the digital input and output options section for details. charger modes input current limit the vinx input current limit is controlled via the internal i 2 c ilim bits. the input current limit can also be controlled via the dig_io1 pin (if factory programmed to do so) as outlined in table 9. any change in the i 2 c default from 100 ma dominates over the pin setting. table 9. dig_io1 operation dig_io1 function 0 100 ma input current limit or i 2 c programmed value 1 500 ma input current limit or i 2 c programmed value (or reprogrammed i 2 c value from 100 ma default) usb compatibility the adp5061 features an i 2 c programmable input current limit to ensure compatibility with the requirements listed in table 10. the current limit defaults to 100 ma to allow compatibility with a usb host or hub that is not configured. the i 2 c register default is 100 ma. an i 2 c write command to the ilim bits override the dig_iox pins, and the i 2 c register default value can be reprogrammed for alternative requirements. when the input current-limit feature is used, the available input current may be too low for the charger to meet the programmed charging current, i chg , thereby reducing the rate of charge and setting the vin_ilim flag. when connecting voltage to vinx without the proper voltage level on the battery side, the high voltage blocking mechanism is in a state wherein it draws only the current of <1 ma until v in reaches the vin_ok level. the adp5061 charger provides support for the following con- nections through the single connector vinx pin (see table 10). table 10. input current compatibility with standard usb limits mode standard usb limit adp5061 function usb (china only) 100 ma limit for standard usb host or hub 100 ma input current limit or i 2 c programmed value 300 ma limit for chinese usb specification 300 ma input current limit or i 2 c programmed value usb 2.0 100 ma limit for standard usb host or hub 100 ma input current limit or i 2 c programmed value 500 ma limit for standard usb host or hub 500 ma input current limit or i 2 c programmed value usb 3.0 150 ma limit for superspeed usb 3.0 host or hub 150 ma input current limit or i 2 c programmed value 900 ma limit for superspeed, high speed usb host or hub charger 900 ma input current limit or i 2 c programmed value dedicated charger 1500 ma limit for dedicated charger or low/full speed usb host or hub charger 1500 ma input current limit or i 2 c programmed value
adp5061 data sheet rev. 0 | page 18 of 44 trickle charge mode a deeply discharged li - ion cell can exhibit a very low cell voltage , making it unsafe to charge the cell at high current rates. the adp5061 charger uses a trickle charge mode to reset the battery pack protection circuit and lift the cell voltage to a safe level for fast charging. a cell with a voltage below v trk_dead is charged with the trickle mode current, i trk_dead . during trickle charging mode, the charger_status bits are set. during trickle charging , the iso_sx node is regulated to v iso_strk by the ldo and the battery isolation fet is off, which means that the battery is isolated from the system power supply. trickle charge mode timer the duration of trickle charge mode is monitored to ensure that the battery is revived from its deeply discharged state. if trickle charge mode runs for longer than 60 minutes without the cell voltage reaching v trk_dead , a fault condition is assumed and charg ing stops. the fault condition is asserted on the charger_status bits , allowing the user to initiate the fault recovery procedure specified in the fault recovery section. weak charge mode (constant current) when the battery voltage exceeds v trk_dead but is less than v weak , the charger switches to intermediate charge mode. during the weak charge mode, the battery voltage is too low to allow the full system to power - up. because of the low battery level, the usb transceiver cannot be powered and, therefore, cannot enumerate fo r more current from a usb host. conse - quently, the usb limit remains at 100 ma. the system microcontroller may or may not be powered by the charger output voltage (v iso_sfc ), depending upon the amount of current required by the microcontroller and/or the system archi tecture. when the iso_s x pins power the microcontroller , the battery c harge current (i chg_weak ) cannot be increased above 20 ma to ensure the microcontroller operation (if doing so) , nor can i chg_weak be increased above the 100 ma usb limit. thus, set the battery charging current as follows: ? se t the default 20 ma via the linear trickle charger branch (to ensure that the microprocessor remains alive if powered b y the main charger outpu t, iso_sx). any residual current on the main charger output, iso_sx, is used to charge the batter y. ? during weak c urrent mode, other features may prevent the weak charging current from reaching its full programmed value. isothermal charging mo de or input current limiting for usb compatibility can affect the programmed weak charging current value under certain operatin g conditions. during weak charging, t he iso_sx node is regulated to v iso_sfc by the battery isolation fet. fast charge mode (constant current) when the battery voltage exceeds v trk_dead and v weak , the charger switches to fast charge mode, charging the battery with the constant current, i chg . during fast charge mode (constant current), the charger_status bits are set to 010 . during constant current mode, other features may prevent the current, i chg , from reaching its full programmed value. isothermal cha rging mode or input current limiting for usb compatibility can affect the value of i chg under certain oper - ating conditions. the voltage on iso_sx is regulated to stay at v iso_sfc by the battery isolation fet when v iso_b < v iso_sfc . fast charge mode (const ant voltage) as the battery charges, its voltage rises and approaches the termi - nation voltage, v trm . the adp5061 charger monitors the voltage on the bat_sns pin to determine when charging should end. however, the internal esr of the battery pack , combined with the printed circuit board ( pcb ) and other parasitic series resistances creat es a voltage drop between the sense point at the bat_sns pin and the cell terminal. to compensate for this and ensure a fully charged cell, the adp5061 enters a constant voltage charging mode when the termination voltage is detected on the bat_sns pin. the adp5061 reduces charge current grad ually as the cell continues to charge, maintaining a voltage of v trm on the bat_sns pin. during fast charge mode (constant voltage), the charger_ status register is set. fast charge mode timer the duration of fast charge mode is monitored to ensure that th e battery is charging correctly. if the fast charge mode runs for longer than t chg without the voltage at the bat_sns pin reaching v trm , a fault condition is assumed and charging stops. the fault condition is asserted on the charger_status bits allowing the user to initiate the fault recovery procedure as specified in the fault recovery section. if the fast charge mode runs for longer than t chg , and v trm ha s been reached on the bat_sns pin but the charge current has not yet fallen below i end , charging stops. no fault condi tion is asserted in this circumstance and charging resumes as normal if the recharge threshold is breached. watchdog timer the adp5061 charger features a programmable watchdog timer function to ensure charging is under the control of the processor. the watchdog timer starts running when the adp5061 ch a rger determines that the processor should be operational, that is, when the processor sets the reset_wd bit for the first time or when t he battery voltage is greater than the weak battery threshold , v weak . when the watchdog timer has been triggered, it mu st be reset regularly within the watchdog timer period, t wd . while in charger mode, i f the watchdog timer expires without being reset , the adp5061 charger assumes that there is a software problem and triggers t he safety timer, t safe . for more infor mation , see the safety timer section.
data sheet adp5061 rev. 0 | page 19 of 44 safety timer while in charger mode, i f the watchdog timer expires , the adp5061 charger initiates the safety timer, t safe (see the watchdog timer section ). if the processor has pr ogrammed charging parameters by the time the ch arger initiates the safety timer , the i lim is set to the default value. charg ing continues for a period of t safe , and then the charger switches off and sets the charger_status bits . charge complete the adp5061 charger monitors the charging current while in constant voltage fast charge mode. if the current falls below i end and remains below i end for t end , charging stops and the chdone flag is set. if the charging current falls below i end for less than t end and t hen rises above i end again, the t end timer resets. recharge after the detection of charge complete, and the cessation of charging, the adp5061 charger monitors the bat_sns pin as the battery discharges through normal use. if the bat_sns pin voltage falls to v rch , the charger reactivates charging. under most circumstances, triggering the recharge threshold results in the charger starting directly into fast charge constant voltage mode. the recharge function can be disabled in i 2 c, but a status bit (r egister 0x0c , b it d3) inform s the system that a recharge cycle is required. ic enable/disable the adp5061 ic can be disabled by the dig_io2 digi ta l input pin (if factory programmed to do so) or by the i 2 c registers. all internal control circuits are disab led when the ic is disabled. disabling the ic1 option can also control the state s of the ldo fet and the battery isolation fet. it is critical to note that during the disable ic1 mode, a high voltage at vinx pass es to the i nternal supply voltage because all of the internal control circuits are disabled. the vinx supply voltage must fulfill the following condition : v iso_b < vinx < 5.5 v battery charging enable/disable the adp5061 c harging function can be disabled by setting the i 2 c en_chg bit to low. the ldo to the system still operates under this circumstance and can be set in i 2 c to th e default or i 2 c programmed s ystem voltage from 4.3 v to 5.0 v (see the relevant i 2 c register description for full details). the adp5061 c harging function can also be controlled via one of the external dig_iox pins (if factory programmed to do so). any change in the i 2 c en_chg bit takes precedence over the pin setting. battery voltage limit to prevent charging the battery monitor of the adp5061 charger can be confi gured to m onitor batte ry voltage and prevent charging when the battery voltage is higher than v chg_vlim (typically 3.7 v) during charging start - up (enabled by en_chg or dig_io3). this function can prevent unnecessary charging of a half discharged battery a nd, as such, can extend the lifetime of the li - ion battery cell. charging start s automatically when the battery voltage drops below v chg_vlim and continues through full charge cycle until the battery voltage reaches v trm (typically 4.2 v). by default , the charging voltage limit is disabled and it can be enabled from i 2 c r egister 0x08, b it en_chg_vlim. sys_en output the adp5061 features a sys_en open - drain fet to enable the system until the battery is at the mini mum required level for guaranteed system start - up. when there are minimum battery voltage and/or minimum battery charge level requirements, the operatio n of sys_en can be set by i 2 c programming. the sys_en operation c an be factory programmed to four different operating conditions as described in table 11 . table 11 . sys_en m ode d escriptions sys_en mode selection description 00 sys_en is activated when ldo is active and system voltage is available . 01 sys_en is activated by the iso_bx voltage , b attery charging mode . 10 sys_en is activated and the i solation fet is disabled when the battery drops below v weak . this option is active, when vinx = 0 v and the battery monitor is activated from register 0x07, bit d5 (en_bmon). 11 sys_en is active in ldo mode when the charger is disabled. sys_en is active in charging mode when iso_bx v weak . indicator led output (iled) the iled is an open - drain output for indicator led connection. optionally, the iled output can be used as a status output for a microcontroller. indicator led modes are shown in table 12. table 12 . indicator led operation m odes adp5061 mode iled m ode on/ off t ime ic o ff off ldo mode off off ldo mode on off charge m ode continuously on timer e rror (t trk , t chg , t safe ) blinking 167 ms/833 ms overt emperature (t sd ) blinking 1 sec/ 1 sec
adp5061 data sheet rev. 0 | page 20 of 44 thermal management isothermal charging the adp5061 includes a thermal feedback loop that limits the charge current when the die temperature exceeds t lim (typically 115c). as the on-chip power dissipation and die temperature increase, the charge current is automatically reduced to maintain the die temperature within the recommended range. as the die temperature decreases due to lower on-chip power dissipation or ambient temperature, the charge current returns to the pro- grammed level. during isothermal charging, the therm_lim i 2 c flag is set to high. this thermal feedback control loop allows the user to set the programmed charge current based on typical rather than worst case conditions. the adp5061 does not include a thermal feedback loop to limit iso_sx load current in ldo mode. if the power dissipated on chip during ldo mode causes the die temperature to exceed 130c, an interrupt is generated. if the die temperature continues to rise beyond 140c, the device enters into thermal shutdown. thermal shutdown and thermal early warning the adp5061 charger features a thermal shutdown threshold detector. if the die temperature exceeds t sd , the adp5061 charger is disabled, and the tsd 140c bit is set. the adp5061 charger can be reenabled when the die temperature drops below the t sd falling limit and the tsd 140c bit is reset. to reset the tsd 140c bit, write to the i 2 c fault register 0x0d or cycle the power. before die temperature reaches t sd , the early warning bit is set if t sdl is exceeded. this allows the system to accommodate power consumption before thermal shutdown occurs. fault recovery before performing the following operation, it is important to ensure that the cause of the fault has been rectified. to recover from a charger fault (when the charger_status = 110), cycle power on vinx or write high to reset the i 2 c fault bits in the fault register. battery isolation fet the adp5061 charger features an integrated battery isolation fet for power path control. the battery isolation fet isolates a deeply discharged li-ion cell from the system power supply in both trickle and fast charge modes, thereby allowing the system to be powered at all times. when vinx is below v vin_ok , the battery isolation fet is in full conducting mode. the battery isolation fet is off during trickle charge mode. when the battery voltage exceeds v trk , the battery isolation fet switches to the system voltage regulation mode. during system voltage regulation mode, the battery isolation fet maintains the v iso_sfc voltage on the iso_sx pins. when the battery voltage exceeds v iso_sfc , the battery isolation fet is in full conducting mode. the battery isolation fet supplements the battery to support high current functions on the system power supply. when voltage on iso_sx drops below iso_bx, the battery isolation fet enters into full conducting mode. when voltage on iso_sx rises above iso_bx, the isolation fet enters regulating mode or full conduction mode, depending on the li-ion cell voltage and the linear charger mode. battery detection battery voltage level detection the adp5061 charger features a battery detection mechanism to detect an absent battery. the charger actively sinks and sources current into the iso_bx/bat_sns node, and voltage vs. time is detected. the sink phase is used to detect a charged battery, whereas the source phase is used to detect a discharged battery. the sink phase (see figure 30) sinks i sink current from the iso_bx/ bat_sns pins for a time period, t batok . if the bat_sns pin is below v batl when the t batok timer expires, the charger assumes no battery is present, and starts the source phase. if the bat_sns exceeds the v batl voltage when the t batok timer expires, the charger assumes the battery is present and begins a new charge cycle. the source phase sources i source current to iso_bx and the bat_sns pin for a time period, t batok . if bat_sns pin exceeds v bath before the t batok timer expires, the charger assumes that no battery is present. if the bat_sns does not exceed the v bath voltage when the t batok timer expires, the charger assumes that a battery is present and begins a new charge cycle.
data sheet adp5061 rev. 0 | page 21 of 44 f igure 30 . sink phase figure 31 . trickle charge battery (iso_bx) s hort d etection a battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled. on commencing trickle char ging, the adp5061 charger moni - tors the battery voltage. if this battery voltage does not exceed v bat_shr within the specified timeout period, t bat_shr , a fault is declared and the charger is stopped by turning the battery isolation fet off , but the system voltage is maintained at v iso_strk by the linear regulator. after source phase, if the iso_bx or bat_sns level remains below v bath , either the battery voltage is low or the battery node can be shorted. because the battery voltage is low, trickle charging mode is initiated (see figure 31 ). if the bat_sns level remains below v bat_shr after t bat_shr has elapsed, the adp5061 assumes that the battery n ode is shorted. the trickle charge branch is acti ve during the battery short scenario , and trickle charge current to the battery is maintained until the 60 - minute tr ickle charge mode timer expires . battery pack tempera ture sensing battery thermistor input the adp5061 charger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. the thr pin provides an on and off switching current source that should be connected directly to the batter y pack thermistor terminal. the activation interval of the thr current source is 167 ms. the battery pack temperature sensing can be controlled by i 2 c, using the conditions shown in table 13 . note that the i 2 c register default setting for en_thr (register 0x07) is 0 = temperature sensing off. table 13 . thr input function conditions thr function vinx v iso_b open or v in = 0 v to 4.0 v <2.5 v off open or v in = 0 v to 4.0 v >2.5 v off, controlled by i 2 c 4.0 v to 6.7 v don't care always on if the battery pack thermistor is not connected directly to the thr pin, a 10 k? (tolerance 20%) dummy resistor must be connected between the thr input and gnd. leaving the thr pin open results in a false detection of the battery temper ature being <0c a nd charging is disabled. the adp5061 charger monitors the voltage in the thr pin and suspends charging if the current is outside the range of less than 0c or greater than 60c. the adp5061 charger is designed for use with an ntc thermistor in the battery p ack with a nominal room tempera ture value of either 10 k? at 25c or 100 k? at 25c, which is selected by factory programming . the adp5061 charger is designed for use with an ntc thermistor in the battery pack with a temperatur e coefficient curve (beta). factory programming supports eight beta values covering a range from 3150 to 4400 (see table 44). open iso_bx sink phase logic status open or short t bat_ok v batl i sink iso_bx open open logic status source phase t bat_ok v ba th i source 10544-030 i source short sink phase source phase trickle charge iso_bx short iso_bx short iso _b x logi c status open or short t bat_ok logi c status short or lo w ba tt ery t bat_ok logi c status short t bat_shr v batl v bath v bat_shr i trk_dead i sink 10544-031
adp5061 data sheet rev. 0 | page 22 of 44 jeita li - ion battery temperature charging specification the adp5061 is compliant with the jeita1 and jeita2 li - ion battery charging temperature specifications as outlined in table 14 and in table 16, respectively. jeita function can be enabled via the i 2 c interface and , optionally , the jeita1 or jeita2 function can be selected in i 2 c. alternatively , the jeita1 or jeita2 can be set as enabled to default by factory programming. when the adp5061 identifies a hot or cold battery condition, the adp5061 takes the following actions: ? stops charging the battery. ? connects or enables t he battery isolation fet such that the adp5061 continues in ldo mode. table 14 . jeita1 s pecifications parameter symbol conditions min max unit jeita1 cold temperature limits i jeita_cold no battery charging occurs 0 c jeita1 cool temperature limits i jeita_cool battery charging occurs at approx imately 50% of programmed level see table 15 for specific charging current reduction levels 0 10 c jeita1 typical tempera ture limits i jeita_typ normal battery charging occurs at default/programmed levels 10 45 c jeita1 warm temperature limits i jeita_warm battery termination voltage (v trm ) is reduced by 100 mv from programmed value 45 60 c jeita1 hot temperature limits i jeita_hot no battery charging occurs 60 c table 15 . jeita1 reduced charge current levels, battery cool temperature ichg[4:0] (d efault) ichg jeita1 ichg[4:0] (d efault) ichg jeita1 00000 = 50 ma 50 ma 01100 = 650 ma 300 ma 00001 = 100 ma 50 ma 01101 = 700 ma 350 ma 00010 = 150 ma 50 ma 01110 = 750 ma 350 ma 00011 = 200 ma 100 ma 01111 = 800 ma 400 ma 00100 = 250 ma 100 ma 10000 = 850 ma 400 ma 00101 = 300 ma 150 ma 10001 = 900 ma 450 ma 00110 = 350 ma 150 ma 10010 = 950 ma 450 ma 00111 = 400 ma 200 ma 10011 = 1000 ma 500 ma 01000 = 450 ma 200 ma 10100 = 1050 ma 500 ma 01001 = 500 ma 250 ma 10101 = 1100 ma 550 ma 01010 = 550 ma 250 ma 10110 = 1200 ma 600 ma 01011 = 600 ma 300 ma 10111 = 1300 ma 650 ma table 16 . jeita2 specifications parameter symbol conditions min max unit jeita2 cold temperature limits i jeita_cold no battery charging occurs 0 c jeita2 cool temperature limits i jeita_cool battery termination voltage (v trm ) is reduced by 100 mv from programmed value 0 10 c jeita2 typical temperature limits i jeita_typ normal battery charging occurs at default/programmed levels 10 45 c jeita2 warm temperature limits i jeita_warm battery termination voltage (v trm ) is reduced by 100 mv from programmed value 45 60 c jeita2 hot temperature limits i jeita_hot no battery charging occurs 60 c
data sheet adp5061 rev. 0 | page 23 of 44 figure 32 . simplified battery and vin connect flowchart reset all registers power-on reset vinok no no no no no ic off enable ldo to charging-mode enable charger low battery chg ldo mode system off yes yes yes yes yes yes no enable charger v bat_sns < v chg_vlim 10544-032
adp5061 data sheet rev. 0 | page 24 of 44 figure 33. simplified charging mode flowchart to charging mode i vin < i lim temp < t lim yes no no charge complete yes t wd expired yes no trickle charge yes tfault or bad battery yes no no v bat_sns < v trk yes no yes no no vinok vinok yes yes t start expired power-down no no no yes yes 1 no no yes yes run battery detection fast charge no yes to ic off v bat_sns = v rch t wd expired t safe or t trk expired i out < i end v bat_sns < v trk watchdog expired start t safe i bus = 100 ma ibuslim = high i vin = i lim run battery detection thermlim = high temp = t lim t safe or t chg expired watchdog expired start t safe i bus = 100 ma tfault or bad battery 1 see timer specs v bat_sns = v trm cc mode charging cv mode charging 10544-033
data sheet adp5061 rev. 0 | page 25 of 44 i 2 c interface the adp5061 includes an i 2 c-compatible serial interface for control of the charging and ldo functions, as well as for a readback of system status registers. the i 2 c chip address is 0x28 in write mode and 0x29 in read mode. registers values are reset to the default values when the vinx supply falls below the v vin_ok falling voltage threshold. the i 2 c registers also reset when the battery is disconnected and v in is 0 v. the subaddress content selects which of the adp5061 registers is written to first. the adp5061 sends an acknowledgement to the master after the 8-bit data byte has been written (see figure 34 for an example of the i 2 c write sequence to a single register). the adp5061 increments the subaddr ess automatically and starts receiving a data byte at the next register until the master sends an i 2 c stop as shown in figure 35. figure 36 shows the i 2 c read sequence of a single register. adp5061 sends the data from the register denoted by the subaddress and increments the subaddress automatically, sending data from the next regi ster until the master sends an i 2 c stop condition as shown in figure 37. figure 34. i 2 c single register write sequence figure 35. i 2 c multiple register write sequence figure 36. i 2 c single register read sequence figure 37. i 2 c multiple register read sequence subaddress chip address st 0010100 0 0 0 sp adp5061 receives data 0 = write 0 master stop adp5061 ack adp5061 ack adp5061 ack 10544-034 0 = write chip address st 0010100 0 0 0 sp adp5061 receives data to register n 0 master stop 0 adp5061 receives data to register n + 1 0 adp5061 receives data to last register adp5061 ack adp5061 ack adp5061 ack adp5061 ack adp5061 ack subaddress register n 10544-035 st st sp 0 = write subaddress chip address 0010100 0 0 1 adp5061 sends data 0 master stop chip address 0010100 0 1 = read 1 0 adp5061 ack adp5061 ack adp5061 ack master ack 10544-036 st st sp 0 = write master stop 1 = read subaddress register n chip address 0010100 0 0 0 adp5061 sends data of register n 0 master ack 0 adp5061 sends data of register n + 1 master ack 1 adp5061 sends data of last register master ack chip address 0010100 0 1 0 adp5061 ack adp5061 ack adp5061 ack 10544-037
adp5061 data sheet rev. 0 | page 26 of 44 i 2 c register map see the factory programmable options section for program ming option details. note that a blank cell indicates a bit that is not used. table 17. i 2 c register map register d7 d6 d5 d4 d3 d2 d1 d0 addr. name 0x00 manufac - turer and model id manuf m odel 0x01 silicon revision rev 0x02 vinx pins settings ilim 1 0x03 termina tion settings vtrm 1 , 2 chg_vlim[1:0] 1 , 2 0x04 charging current ichg 1 , 2 itrk_dead 1 0x05 voltage threshold s dis_rch 1 , 3 vrch 1 vtrk_dead 1 , 3 vweak 1 0x06 timer settings en_tend 1 en_chg_timer 1 chg_tmr_period 1 en_wd 1 , 3 wd_period 1 reset_wd 0x07 functional s ettings 1 dis_ic1 1 en_bmon 1 en_thr 1 dis_ldo 1 en_eoc 1 en_chg 1 0x08 functional s ettings 2 en_jeita 1 , 3 jeita_select 1 , 3 en_chg_vlim 1 , 3 ideal_diode[1:0] 1 , 3 vsystem[2:0] 1 , 3 0x09 interrupt enable en_therm_lim_int en_wd_int en_tsd_int en_thr_int en_bat_int en_chg_int en_vin_int 0x0a interrupt active therm_lim_int wd_int tsd_int thr_int bat_int chg_int vin_int 0x0b charger status 1 vin_ov vin_ok vin_ilim therm_lim chdone charger_status 0x0c charger status 2 thr_status rch_lim_info battery_status 0x0d fault register bat_shr 1 tsd 130 c 1 tsd 140 c 1 0x10 battery short tbat_shr 1 vbat_shr 1 0x11 iend iend 1 , 3 c/20 eoc 1 c/10 eoc 1 c/5 eoc 1 sys_en_set 1 , 3 1 these bits reset to default i 2 c values when vinx is connected or disconnected. 2 the default i 2 c values of these bits are partially factory pro grammable. 3 the default i 2 c values of these bits are fully factory programmable.
data sheet adp5061 rev. 0 | page 27 of 44 register bit descrip tions in table 18 through table 33 , the following abbreviations are used: r is read only, w is write only, r/w is read/w rite, and n/a means not applicable. table 18 . manufacturer and model id, register address 0x00 bit no. bit name access default description [ 7:4 ] manuf[3:0] r 0001 the 4 - bit manufacturer identification bus [ 3:0 ] model[3:0] r 1001 the 4- bit model identification bus table 19. silicon revision register, register address 0x01 bit no. bit name access default description [ 7:4 ] not used r [ 3:0 ] rev[3:0] r 0100 the 4 - bit sili con revision identification bus table 20. vinx settings register, register address 0x02 bit no. bit name access default description [ 7:5 ] not used r 4 rfu r/w 0 reserved for future use. [ 3:0 ] ilim[3:0] r/w 0000 = 100 ma vinx input current - limit programming bus. the current into vinx can be limited to the following programmed values: 0000 = 100 ma. 0001 = 150 ma. 0010 = 200 ma. 0011 = 250 ma. 0100 = 300 ma. 0101 = 400 ma. 0110 = 500 ma. 0111 = 600 ma. 1000 = 700 ma. 1001 = 800 ma. 1010 = 900 ma. 1011 = 1000 ma. 1100 = 1200 ma. 1101 = 1500 ma. 1110 = 1800 ma. 1111 = 2100 ma.
adp5061 data sheet rev. 0 | page 28 of 44 table 21 . termination settings, register address 0x03 bit no. bit name access default description [ 7:2 ] vtrm[5:0] r/w 100011 = 4.20 v termination voltage programming bus. the values of the float voltage can be programmed to the following values: 001111 = 3.80 v. 010000 = 3.82 v. 010001 = 3.84 v. 010010 = 3.86 v. 010011 = 3.88 v. 010100 = 3.90 v. 010101 = 3.92 v. 010110 = 3.94 v. 010111 = 3.96 v. 011000 = 3.98 v. 011001 = 4.00 v. 011010 = 4.02 v. 011011 = 4.04 v. 011100 = 4.06 v. 011101 = 4.08 v. 011110 = 4.10 v. 011111 = 4.12 v. 100000 = 4.14 v. 100001 = 4.16 v. 100010 = 4.18 v. 100011 = 4.20 v. 100100 = 4.22 v. 100101 = 4.24 v. 100110 = 4.26 v. 100111 = 4.28 v. 101000 = 4.30 v. 101001 = 4.32 v. 101010 = 4.34 v. 101011 = 4.36 v. 101100 = 4.38 v. 101101 = 4.40 v. 101110 = 4.42 v. 101111 = 4.44 v. 110000 = 4.44 v. 110001 = 4.46 v. 110010 = 4.48 v. 110011 to 111111 = 4.50 v. [ 1:0 ] chg_vlim[1:0] r/w 10 = 3.7 v charging voltage limit programming bus. the values of the charging voltage limit can be programmed to the following values: 00 = 3.2 v . 01 = 3.4 v . 10 = 3.7 v . 11 = 3.8 v .
data sheet adp5061 rev. 0 | page 29 of 44 table 22 . charging current settings, register address 0x04 bit no. bit name access default description 7 not used r 6 not used r [ 5:2 ] ichg[4:0] r/w 01110 = 750 ma fast charge current programming bus. the values of the constant current charge can be programmed to the following values: 00000 = 50 ma. 00001 = 100 ma. 00010 = 150 ma. 00011 = 200 ma. 00100 = 250 ma. 00101 = 300 ma. 00110 = 350 ma. 00111 = 400 ma. 01000 = 450 ma. 01001 = 500 ma. 01010 = 550 ma. 01011 = 600 ma. 01100 = 650 ma. 01101 = 700 ma. 01110 = 750 ma. 01111 = 800 ma. 10000 = 850 ma. 10001 = 900 ma. 10010 = 950 ma. 10011 = 1000 ma. 10100 = 1050 ma. 10101 = 1100 ma. 10110 = 1200 ma. 10111 to 11111 = 1300 ma. [ 1:0 ] itrk_dead[1:0] r/w 10 = 20 ma trickle and weak charge current programming bus. the values of the trickle and weak charge currents can be programmed to the following values: 00 = 5 ma. 01 = 10 ma. 10 = 20 ma. 11 = 80 ma. table 23 . voltage thresholds, register address 0x05 bit no. bit name access default description 7 dis_rch r/w 0 = recharge enabled 0 = recharge enabled. 1 = recharge disabled. [ 6:5 ] vrch[1:0] r/w 11 = 260 mv recharge voltage programming bus. the values of the recharge threshold can be programmed to the following values (note that the recharge cycle can be disabled in i 2 c by the dis_rch bit): 00 = 80 mv. 01 = 140 mv. 10 = 200 mv. 11 = 260 mv.
adp5061 data sheet rev. 0 | page 30 of 44 bit no. bit name access default description [ 4:3 ] vtrk_dead[1:0] r/w 01 = 2.5 v trickle to fast charge dead battery voltage programming bus. the values of the trickle to fast charge threshold can be programmed to the following values: 00 = 2.0 v. 01 = 2.5 v. 10 = 2.6 v. 11 = 2.9 v. [ 2:0 ] vweak[2:0] r/w 011 = 3.0 v weak battery voltage rising threshold. 000 = 2.7 v. 001 = 2.8 v. 010 = 2.9 v. 011 = 3.0 v. 100 = 3.1 v. 101 = 3.2 v. 110 = 3.3 v. 111 = 3.4 v. table 24. timer settings, register address 0x06 bit no. bit name access default description [ 7:6 ] not used 5 en_tend r/w 1 0 = c harge complete timer , t end , disabled . a 31 ms deglitch timer remain s on . 1 = charge complete timer enabled. 4 en_chg_timer r/w 1 0 = trickle/fast charge timer dis abled. 1 = trickle/fast charge timer en abled. 3 chg_tmr_period r/w 1 trickle and fast charge timer period. 0 = 30 sec t rickle charge timer and 300 minute fast charge timer . 1 = 60 sec t rickle charge timer and 600 minute fast charge timer . 2 en_wd r/w 0 0 = w atchdog timer is disabled even when bat_sns exceeds v dead . 1 = w atchdog timer safety timer is enabled. 1 wd_period r/w 0 watchdog safety timer period. 0 = 32 sec w atchdog timer and 40 minute safety timer . 1 = 64 sec w atchdog timer and 40 minute safety timer . 0 reset_wd w 0 when reset_wd is set to logic h igh by i 2 c , the watchdog safety timer is reset . table 25 . functional settings 1 , register address 0x07 bit no. bit name access default description 7 not used 6 dis_ic1 r/w 0 0 = n ormal operation. 1 = the adp5061 is disabled, v vin must be v iso_b < v vin < 5.5 v. 5 en_bmon r/w 0 0 = w hen v vin < v vin_ok , the battery monitor is disabled. when v vin = 4.0 to 6.7 v, the battery monitor is enabled regardless of the en_bmon state . 1 = the battery monitor is enabled even when the voltage at the vinx pins is below v vin_ok . 4 en_thr r/w 0 0 = w hen v vin < v vin_ok , the thr current source is disabled. when v vin = 4.0 v to 6.7 v, the thr current source is enabled regardless of the en_thr state. 1 = thr current source is enabled even when the voltage at the vinx pins is below v vin_ok . 3 dis _ ldo r/w 0 0 = ldo is enabled. 1 = ldo is off. in addition, if en_chg = low, the battery isolation fet is on. if en_chg = high , the battery isolation fet is off.
data sheet adp5061 rev. 0 | page 31 of 44 bit no. bit name access default description 2 en_eoc r/w 1 0 = e nd of charge not allowed. 1 = end of charge allowed. 1 not used 0 en_chg r/w 0 0 = b attery charging is disabled. 1 = battery charging is enabled. table 26 . functional settings 2 , register address 0x08 bit no. bit name access default description 7 en_jeita r/w 0 = jeita disabled 0 = jeita compliance of the li - ion temperature battery charging specifications is disabled. 1 = jeita compliance enabled. 6 jeita_select r/w 0 = jeita1 0 = jeita1 is selected. 1 = jeita2 is selected. 5 en_chg_vlim r/w 0 0 = c harging voltage limit disabled. 1 = voltage limit activated. the charger prevents charging until the battery voltage drops below the v chg_vlim threshold. [ 4:3 ] ideal_diode[1:0] r/w 00 00 = ideal diode operates always when v iso_s < v iso_b . 01 = ideal diode operates when v iso_s < v iso_b and v bat_sns > v weak . 10 = ideal diode is disabled. 11 = ideal diode is disabled. [ 2:0 ] vsystem[2:0] r/w 000 = 4.3 v s ystem voltage programming bus. the values of the system voltage can be programmed to the following values: 000 = 4.3 v. 001 = 4.4 v. 010 = 4.5 v. 011 = 4.6 v. 100 = 4.7 v. 101 = 4.8 v. 110 = 4.9 v. 111 = 5.0 v. table 27. interrupt enable register, register address 0x09 bit no. mnemonic access default description 7 not used 6 en_therm_lim_int r/w 0 0 = i sothermal charging interrupt is disabled. 1 = isothermal charging interrupt is enabled. 5 en_wd_int r/w 0 0 = w atchdog alarm interrupt is disabled. 1 = watchdog alarm interrupt is enabled. 4 en_tsd_int r/w 0 0 = o vertemperature interrupt is disabled. 1 = overtemperature interrupt is enabled. 3 en_thr_int r/w 0 0 = thr temperature thresholds interrupt is disabled. 1 = thr temperature thresholds interrupt is enabled. 2 en_bat_int r/w 0 0 = b attery voltage thresholds interrupt is disabled. 1 = battery voltage thresholds interrupt is enabled. 1 en_chg_int r/w 0 0 = c harger mode change interrupt is disabled. 1 = charger mode change interrupt is enabled. 0 en_vin_int r/w 0 0 = vinx pin voltage thresholds interrupt is disabled. 1 = vinx pin voltage thresholds interrupt is enabled.
adp5061 data sheet rev. 0 | page 32 of 44 table 28 . interrupt active register, register address 0x0a bit no. mnemonic access default description 7 not used 6 therm_lim_int r 0 1 = i ndicates an interrupt caused by isothermal charging. 5 wd_int r 0 1 = i ndicates an interrupt caused by the watchdog alarm. the watchdog timer expires within 2 sec or 4 sec , depending on the watch dog period setting of 32 sec or 64 sec , respectively. 4 tsd_int r 0 1 = i ndicates an interrupt caused by an overtemperature fault. 3 thr_int r 0 1 = i ndicates an interrupt caused by thr temperature thresholds. 2 bat_int r 0 1 = i ndicates an interrupt caused by battery voltage thresholds. 1 chg_int r 0 1 = i ndicates an interrupt caused by a charger mode change. 0 vin_int r 0 1 = i ndicates an interrupt caused by vin voltage thresholds. table 29. charger status register 1, register address 0x0b bit no. mnemonic access default description 7 vin_ov r n/a 1 = i ndicates that the voltage at the vinx pins exceeds v vin_ov . 6 vin_ok r n/a 1 = i ndicates that the voltage at the vinx pins exceeds v vin_ok . 5 vin_ilim r n/a 1 = i ndicates that the current into a vinx pin is limited by the high voltage blocking fet and the charger is not running at the full programmed i chg . 4 therm_lim r n/a 1 = i ndicates that the charger is not running at the full programmed i chg but is limited by the die temperature. 3 chdone r n/a 1 = i ndicates the end of charge cycle has been reached. this bit latches on, in that it does not reset to low when the v rch threshold is breached. [ 2:0 ] chager_status[2:0] r n/a charger status bus. 000 = off. 001 = trickle charge. 010 = fast charge (cc mode). 011 = fast charge (cv mode). 100 = charge complete. 101 = ldo mode. 110 = trickle or fast charge timer expired. 111 = battery detection.
data sheet adp5061 rev. 0 | page 33 of 44 table 30. charger status register 2, register address 0x0c bit no. mnemonic access default description [ 7:5 ] thr_status[2:0] r n/a thr pin status. 000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor ok. 4 not u sed r n/a 3 rch_lim_info r n/a the recharge limit information function is activated when dis_rch is logic high and the charger_status[2:0] = 100 (binary). the statu s bit informs the system that a recharge cycle is required. 0 = v bat_sns > v rch . 1 = v bat_sns < v rch . 2:0 battery_status[2:0] r battery status bus. 000 = battery monitor off. 001 = no battery. 010 = v bat_sns < v trk . 011 = v trk v bat_sns < v weak . 100 = v bat_sns v weak . table 31 . fault register 1 , register address 0x0d bit no. mnemonic access default description [ 7:4 ] not u sed 3 bat_shr r/w 0 1 = i ndicates detection of a battery short. 2 not u sed r/w 1 tsd 130c r/w 0 1 = i ndicates an overtemperature (lower) fault . 0 tsd 140c r/w 0 1 = i ndicates an overtemperature fault . 1 to reset the fault bits in the fault register, cycle power on vinx or write high to the corresponding i 2 c bit. table 32 . battery short, register address 0x10 bit no. mnemonic access default description [ 7:5 ] tbat_shr[2:0] r/w 100 = 30 sec battery short timeout timer. 000 = 1 sec. 001 = 2 sec. 010 = 4 sec. 011 = 10 sec. 100 = 30 sec. 101 = 60 sec. 110 = 120 sec. 111 = 180 sec. [ 4:3 ] not used r/w [ 2:0 ] vbat_shr[2:0] r/w 100 = 2.4 v battery short voltage threshol d level. 000 = 2.0 v. 001 = 2.1 v. 010 = 2.2 v. 011 = 2.3 v. 100 = 2.4 v. 101 = 2.5 v. 110 = 2.6 v. 111 = 2.7 v.
adp5061 data sheet rev. 0 | page 34 of 44 table 33. iend register , register address 0x11 bit no. mnemonic access default description [ 7:5 ] iend[2:0] r/w 010 = 52.5 ma termination current programming bus. the values of the termination current can be programmed to the following values: 000 = 12.5 ma. 001 = 32.5 ma. 010 = 52.5 ma. 011 = 72.5 ma. 100 = 92.5 ma. 101 = 117.5 ma. 110 = 142.5 ma. 111 = 170.0 ma. 4 c/20 eoc r/w the c/20 eoc bit has priority over the othe r settings (c/10 eoc, c/5 eoc, and iend). 1 = t he termination current is ichg/20 with the following limitations: minimum value = 12.5 ma. maximum value = 170 ma. 3 c/10 eoc r/w the c/10 eoc bit has priority over the other termination current settings (iend), but does not have priority over the c/20 eoc setting. 1 = t he termination current is ichg/10 unless c/20 eoc is high. the termination current is limited to the following values: minimum value = 12.5 ma. maximum value = 170 ma. 2 c/5 eoc r/w the c/5 bit has priority over the other termination current settings (iend), but does not have priority over the c/20 eoc setting or the c/10 eoc setting. 1 = t he termination current is ichg / 5 unless the c/20 or the c/10 eoc is high. the termination current is limited to the following values: minimum value = 12.5 ma. maximum value = 170 ma. 1:0 sys_en_set[1:0] r/w 0 selects the operation of the system enable pin (sys_en). 00 = sys_en is activated when ldo is active and the system voltage is available. 01 = sys_en activated by iso_bx voltage , the battery charging mode. 10 = sys_en is activated and the isolation fet is disabled when the battery drops below v weak . 1 11 = sys_en is active in ldo mode when the charger is disabled. sys_en is active in the charging mode when v iso_b v weak . 1 this option is active when vinx = 0 v and the battery monit or is activated from register 0x07, bit d5 (en_bmon).
data sheet adp5061 rev. 0 | page 35 of 44 applications information external components iso_sx (v out ) capacitor selection to obtain stable operation of the adp5061 in a safe way , the combined effective capacitance of the iso_sx capacitor and the system capacitance must not be less than 20 f and must not exceed 100 f at any point during operation. when choosing the capacitor value, it is also important to account for the loss of capacitance due to the output voltage dc bias . ceramic capacitors are manufa ctured with a variety of dielec trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature ra nge and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or higher are recommended for best performance. y5v and z5u dielectrics are not recommended for use w ith any dc - to - dc converter because of their poo r temper ature and dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over the ?40 c to +85c temperature range is assumed to be 15% for an x7r dielectric. the tolerance of the capacitor (tol) is assumed to be 20%, and c out is 30.4 f at 5.0 v, as shown in figure 38 . figure 38 . murata GRM32ER61A476ME20c capacitance vs. bias voltage substituting these values in the equation yields c eff = 34.3 f (1 ? 0.15) (1 ? 0.2) 20.7 f to guarantee the performance of the charger in various operation modes including trickle charge, constant current charge, and constant voltage charge, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capaci - tors be evaluated for each application. splitting iso_sx capacita nce in many application s, the total iso_sx capacitance consist s of a nu mber of capacitors. the system voltage node (iso_sx) usually supplies a single regulator or a number of ics and regulators, each of which requires a capacitor close to its power supply input (see figure 39 ). the capacitance close to the adp5061 iso_sx output should be at least 10 f , as long as the tota l effective capacitance is at least 20 f at any point during operation. figure 39 . splitting iso_sx capacitance iso_bx capacitor selection the iso_bx effective capacitance (including temperature and dc bias effects) must not be less than 10 f at any point during operation. typically, a nominal capacitance of 22 f is required to fulfill the condition at all points of operation. suggestions for an iso_bx capacitor are listed in table 35 . cbp capacitor selection the i nternal supply voltage of the adp5061 is equipped with a noise suppressing capacitor at the cbp terminal. do not a llow cbp capacitance to exceed 14 nf at any point during operation. do not connect any external voltage source, any resistive load , or any other current load to the cbp terminal. suggestions for a cbp capacitor are listed in table 36. 20 25 30 35 40 45 50 55 60 0 1 2 3 4 5 cap ac it anc e (f) dc bias voltage (v) 10544 - 041 adp5061 ic1 ic2 iso_sx vin1 vin2 c in1 c in2 c iso_s 10f c iso_b 10f sum of effective capacitances on iso_sx node 20f + iso_bx 10544-038
adp5061 data sheet rev. 0 | page 36 of 44 vinx capacitor selection according to the usb 2.0 specification, usb peripherals have a detectabl e change in capacitance on vbus when they are attached to a usb port . the peripheral device vbus bypass capacitance must be at least 1 f but not larger than 10 f. the vinx input of the adp5061 is tolerant of voltages as high as 20 v ; however, i f an application requires exposing the vinx input to voltages of up to 20 v, the voltage range of the capacitor must also be above 20 v. suggestions for a vinx capacitor are given in table 37. w hen usi ng ceramic capacitors , a higher voltage range is usually achieved by selecting a component with larger physical dimen - sions. in application s where lower than 20 v at vinx input voltages can be guaranteed, smaller output capacitors can be used accordingly. table 34 . iso_sx capacitor suggestions vendor part number value voltage size murata GRM32ER61A476ME20 47 f 10 v 1210 tdk c3225x5r1a476m 47 f 10 v 1210 table 35 . iso_bx capacitor suggestions vendor part number value voltage size murata grm31cr61a226ke19 22 f 10 v 1206 murata grm31cr60j226me19 22 f 6.3 v 1206 tdk c3216x5r0j226m 22 f 6.3 v 1206 t aiyo - y uden jmk316abj226kl 22 f 6.3 v 1206 table 36 . cbp capacitor suggestions vendor part number value voltage size murata grm15xr71c103ka86 10 n f 16 v 0402 tdk c1005x7r1c103k 10 nf 16 v 0402 table 37 . vinx capacitor suggestions vendor part number value voltage size murata grm21br61e106ma73 10 f 25 v 0805 tdk c2012x5r1e106k 10 f 25 v 0805
data sheet adp5061 rev. 0 | page 37 of 44 pcb layout guideline s figure 40 . reference circuit diagram figure 41 . reference pcb floor p lan c2 vddio d2 e2 d1 e1 b3 d3 c3 a4 a3 b1 e4 c4 b2 vin1:3 cbp scl sda iso_s1:3 iso_b1:3 sys_en agnd dig_io1 dig_io2 dig_io3 thr d4 bat_sns to mcu to mcu to mcu to mcu/nc to mcu/nc charger control block r5 ntc 10k? (optional) connect close to battery + e3 c1 b4 to mcu/nc a1 iled vled a2 vddio r4 10k? r2 1.5k? r1 1.5k? c4 10f grm21br61e106ma73 c1 10nf grm15xr71c103ka86 vin = 4v to 6.7v adp5061 wlcsp20 c3 47f GRM32ER61A476ME20 c2 22f grm31cr60j226me19 10544-039 c bp 10nf c iso_s 47f c iso_b 22 f pgnd iso_b iso_s adp5061 c vin 10f vin 8 mm 5.5mm pgnd 10544-042
adp5061 data sheet rev. 0 | page 38 of 44 power dissipation and thermal considerations charger power dissip ation when the adp5061 charger operates at high ambient tempera - tures and at maximum current charging and loading conditions, the junction tempera ture can reach the max imum allowable operating limit of 125c . when the junction temperature exceeds 140c, the adp5061 turns off , allowing the device to cool down. when the die temperature falls below 110c an d the tsd 140c fault bit in register 0x0d is cleared by an i 2 c write, the adp5061 resumes normal operation. this section provides guidelines to calculate the power dissi - pated in the device to ensure that the adp5061 operates below the maximum allowable junction temperature. to determine the available output current in different operating modes under various operating conditions , the user can reference the following equations: p d = p ldofet + p isofet (1) w here : p ldofet is the power dissipated in the input ldo fet. p isofet is the power dissipated in the battery isolation fet. calculate the p ower dissipation in the ldo fet and the battery isolation fet using equation 2 and equation 3 . p ldofet = ( v in C v iso_s ) ( i chg + i load ) (2) p isofet = ( v iso_s C v iso_b ) i chg (3) w here : v in is the input voltage at the vinx pins. v iso_s is the system voltage at the iso_sx pins. v iso_b is the battery voltage at the iso_bx pins. i chg is the battery charge current. i load is the system load current from the iso_sx pins. ldo mode the system regulation voltage is user programmable from 4.3 v to 5.0 v. in ldo mode (charging disabled, en_chg = low) , calculation of the total power dissipation is simplified , assuming that all current is drawn from the vin x pins and the battery is not shared with iso_sx. p d = ( v in C v iso_s ) i load charging mode in charging mode , the voltage at the iso_sx pins depends on the battery level. when the ba ttery voltage is lower than v iso_sfc (typically 3.8 v) , the voltage drop over the battery isolation fet is higher and the power dissipation must be calculated using e quation 3. when the battery voltage level reaches v iso_sfc , the power dissipation can be calculated using e quation 4. p isofet = r dson _ iso i chg (4) w here : r dson_iso is the on resistance of the battery isolation fet (typically 110 m? during charging) . the thermal control loop of the adp5061 automat ically limit s the charge current to maintain a die temperature below t lim (typically 115c). the most intuitive and practical way to calculate the power dissipation in the adp5061 device is to measure the power dissipated at the input and all of the outputs. perform the measurements at the worst - case conditions (voltages, currents, and temperature). the difference between input and output power is the power that is dissipated in the device. junction temperature in cases where the board temperature, t a , is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + ( p d ja ) (5) the typical ja value for the 20 - bump wlcsp is 46.8c/w (see table 5 ). a very important factor to consider is that ja is based on a 4 - layer, 4 in 3 in, 2.5 oz . cop per board as p er jedec standard , and real applications may use different sizes and layers. it is important to maximize the copper to remove the heat from the device. copper exposed to air dissipates heat better than copper used in the inner layers. if the case temperature can be measured, the junction temperature is calculated by t j = t c + ( p d jc ) (6) where t c is the case temperature and jc is the junction - to - case thermal resistance provided in table 5 . for a wlcsp device, where possible, remove heat from every current carrying bump (vinx, iso_sx, and iso_bx). for example, thermal vias to the board power planes can be placed close to these pins, where available. the reliable operation of the charger can be achieved only if the estimated die junction temperature of the adp5061 (equation 5) is less than 125c. reliability and mean time between failures (mtbf) are great ly affected by increas ing the junction temperature. additional information about product reliability can be found in the adi reliability handbook located at the following url: www.analog.com/reliability_handbook .
data sheet adp5061 rev. 0 | page 39 of 44 factory programmable options charger options table 38 to table 50 list the factory programmable options of the adp5061 . in each of these tables , the selection column represents the default setting of m odel adp5061acbz -2- r7. table 38 . default termination voltage option selection 000 = 4.20 v 000 = 4.20 v 010 = 3.70 v 011 = 3.80 v 100 = 3.90 v 101 = 4.00 v 110 = 4.10 v 111 = 4.40 v table 39 . default fast charge current option selection 000 = 500 ma 001 = 300 ma 010 = 550 ma 011 = 600 ma 100 = 750 ma 100 = 750 ma 101 = 900 ma 110 = 1300 ma 111 = 1300 ma table 40 . default end of charge current option selection 000 = 52.5 ma 000 = 52.5 ma 001 = 72.5 ma 010 = 12.5 ma 011 = 32.5 ma 100 = 142.5 ma 101 = 167.5 ma 110 = 92.5 ma 111 = 117.5 ma table 41 . default trickle to fast charge threshold option selection 00 = 2.5 v 00 = 2.5 v 01 = 2.0 v 10 = 2.9 v 11 = 2.6 v table 42 . default system voltage option selection 000 = 4.3 v 001 = 4.4 v 010 = 4.5 v 011 = 4.6 v 100 = 4.7 v 101 = 4.8 v 110 = 4.9 v 111 = 5.0 v 111 = 5.0 v table 43 . thermistor resistance option selection 0 = 10 k 0 = 10 k 1 = 100 k table 44 . thermistor beta value option selection 0100 = 3150 0100 = 3150 0101 = 3350 0110 = 3500 0111 = 3650 1000 = 3850 1001 = 4000 1010 = 4200 1011 = 4400 table 45 . dis_ic1 mode select option selection 0 = dic_ic1 mode select, vinx current = 280 a, iso_b can float, no leak to iso_bx 0 1 = dic_ic1 mode select, vinx current = 110 a, supply switch leaks from vinx to iso_bx table 46 . trickle or fast charge timer fault operation option selection 0 = a fter timeout ldo off, charging off 1 = a fter timeout ldo mode active, charging off 1 = ldo mode active
adp5061 data sheet rev. 0 | page 40 of 44 i 2 c register defaults table 47. i 2 c register default settings bit name i 2 c register address, bit location option selection chg_vlim address 0x03 , b it s[ d1 :d0] 0 = limit 3.2 v, 1 = limit 3.7 v 0 = limit 3.2 v dis_rch address 0x05, b it d7 0 = recharge enabled, 1 = recharge disabled 0 = recharge enabled en_wd address 0x06, b it d2 0 = watchdog disabled, 1 = watchdog enabled 0 = disabled dis_ic1 address 0x07, b it d6 0 = not activated, 1 = activated 0 = not activated en_chg address 0x07, b it d0 0 = charging disabled, 1 = charging enabled 0 = charging disabled en_jeita address 0x08, b it d7 0 = jeita disabled, 1 = jeita enabled 0 = jeita disabled jeita_select address 0x08, b it d6 0 = jeita1 charging, 1= jeita2 charging 0 = jeita1 charging en_chg_vlim address 0x08, b it d5 0 = limit disabled, 1 = limit enabled 0 = limit disabled ideal_diode[1:0] address 0x08, b it s[ d4: d3] 00 = i deal diode operates when v iso_s < v iso_b 00 01 = i deal diode operates when v iso_s < v iso_b and v bat_sns > v weak 10 = i deal diode is disabled 11 = i deal diode is disabled digital input and ou tput options table 48. i 2 c address 0x11, b its[d 1: d0] sys_en output default option selection 00 = sys_en is activated when ldo is active and system voltage is available 00 01 = sys_en is activated by iso_bx voltage; b attery charging mode 10 = sys_en is activated and i solation fet is disabled when battery drops below v weak 1 11 = sys_en is active in ldo mode when charger is disabled. sys_en is active in charging mode when v iso_b v weak 1 this option is active when vinx = 0 v and battery monitor is activated from register 0x07, bit d5 (en_bmon).
data sheet adp5061 rev. 0 | page 41 of 44 dig_io1, dig_io2 , and dig_io3 options table 49 . dig_io1 polarity table 50. dig_iox option s option selection 0 = dig_io1 polarity, high active operation 0 = high active 1 = dig_io1 polarity, low active operation option dig_io1 function dig_io2 function dig_io3 function selection 0 000 i vin limit, low = 100 ma, high = 500 ma disable ic1, low = not activated, high = activated lo w = charging disabled, high = charging enabled 000 0 0 010 i vin limit, low = 100 ma, high = 500 ma h igh = i vin limit 1500 ma disable ic1, low = not activated, high = activated 0 011 i vin limit, low = 100 ma, high = 500 ma h igh = i vin limit 1500 ma fas t charge current, low = ichg, high = ichg/ 2 0 100 i vin limit, low = 100 ma, high = 500 ma h igh = i vin limit 1500 ma l ow = ldo active, high = ldo disabled 0 101 i vin limit, low = 100 ma, high = 500 ma h igh = i vin limit 1500 ma low = charging disabled, hig h = charging enabled 0 110 i vin limit, low = 100 ma, high = 500 ma disable recharge l o w = charging disabled, high = charging enabled 0 111 low = charging disabled, high = charging enabled disable ic1, low = not activated, high = activated h igh = d isable recharge 1000 i vin limit, low = 100 ma, high = 500 ma high = i vin limit 1500 ma interrupt output 1001 i vin limit, low = 100 ma, high = 500 ma low = charging disabled, high = charging enabled interrupt output 1010 i vin limit, low = 100 ma, high = 500 ma disable ic1, low = not activated, high = activated interrupt output 1011 i vin limit, low = 100 ma, high = 500 ma high = disable recharge interrupt output 1100 i vin limit, low = 100 ma, high = 500 ma fast charge current, low = ichg, high = ichg/2 interrupt output 1101 i vin limit, low = 100 ma, high = 500 ma low = ldo active, high = ldo disabled interrupt output 1110 high = i vin limit 1500 ma low = charging disabled, high = charging enabled interrupt output 1111 disable ic1, low = not activated, high = activated low = charging disabled, high = charging enabled interrupt output
adp5061 data sheet rev. 0 | page 42 of 44 packaging and ordering information outline dimensions figure 42 . 20 - ball wafer level chip scale package [wlcsp] (cb - 20 - 9) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adp5061acbz -2- r7 C 40c to +125c 20 - ball wlcsp cb -20 -9 adp5061cb - evalz evaluation board 1 z = rohs compliant part. 2 for additional factory programmable options, contact a local analog devices , inc., s ales or distribution representative . a b c d e 2.635 2.595 2.555 2.035 1.995 1.955 1 23 4 bot t om view (bal l side up) top view (bal l side down) bal l a1 identifier 0.50 ref 0.660 0.600 0.540 side view 0.270 0.240 0.210 0.360 0.320 0.280 2.00 ref 1.50 ref coplanarity 0.04 sea ting plane 0.390 0.360 0.330 04-18-2012- a
data sheet adp5061 rev. 0 | page 43 of 44 notes
adp5061 data sheet rev. 0 | page 44 of 44 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10544 -0- 6/12(0) www.analog.com/ adp5061

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